Dr Matthew (Wai-Chung) Tang 鄧偉宗博士

Xilinx Vivado (Webpack) 2017.3 Installation

2022-05-28T09:02:00+00:00

In my Digital System Design module in QMUL EECS, we used the NI DSDB board for lab exercises. The board is very powerful and can be programmed via Xilinx Vivado or NI Labview. In this blog of reminder, I am going to outline the installation process for Xilinx Vivado version 2017.3 which gives the best compatibilty for the DSDB board.

First, download the Vivado HLx 2017.3: WebPACK and Editions - Windows Self Extracting Web Installer from the Xilinx website (link above).

Then start the installation by opening the file. Skip the latest version of course by clicking Continue.

If you have not yet got a Xilinx account, follow the links to create one. Enter your credentials here and carry on with Download and Install Now.

Agree the terms of licenses …

Choose the free Vivado HL WebPack version …

Double check the installation locations and so on.

Wait patiently till the installation finishes …

During the process, you will be prompted to install some Windows drivers for debugging cables.

That should work till the end of the installation. Next time, I will share an example of a simple design that demonstrate the basic input and output devices available on the DSDB board.

Keil uVision in Virtual Machine

2022-05-02T13:14:00+00:00

This is a note to myself and my students about installing Keil uVision via Virtual Machines.

1. Virtual Box

This instruction is intended for Ubuntu Linux, but the steps should be similar for MacOS

2a. Windows XP

Link to VM

On WinXP, download and install v5.18 instead of latest version.

2b. Windows 10 (Slower on most machines)

The Keil ARM-MDK only supports Windows OS. For Linux/Mac users, the only way for running that for our lab exercises is to use a Virtual Machine (VM). The following steps will help you set up a free Windows 10 (Win10) VM using VirtualBox and run Keil uVision inside.

Download and install an official Microsoft Windows 10 Virtual Machine: Windows 10 with Legacy Microsoft Edge and Internet Explorer 11 (6.7 GB)
Install VirtualBox
Unzip the file from step 1 and import that in VirtualBox.
Start the Win10. Transfer the Keil installer (+ software pack) to the VM (e.g. Drag-n-Drop). Install Keil uVision and software pack inside the VM.
Test running Keil uVision with our lab files.

Quartus Lite 18.1 Installation

2021-12-17T15:55:00+00:00

In one of my modules, I used the Terasic DE10-Lite FPGA board for labs. This handy, little board can be programmed easily via a USB-A cable as it has the Altera USB-Blaster programmer already. My students found it very useful to verify their digital designs on board.

In this article, I will list the main steps to install the Intel Quartus Lite design software (version 18.1 that DE10-Lite originally asks for, despite newer versions are known to work well) with ModelSim simulation tool and MAX-10 FPGA support.

First, download the following from the Intel website (link above):

QuartusLiteSetup-18.1.0.625-windows.exe (version may change)
ModelSimSetup-18.1.0.625-windows.exe (version should match with Quartus Lite)
max10-18.1.0625.qdz (MAX-10 FPGA support files)

Then start the installation by opening QuartusLiteSetup-18.1.0.625-windows.exe. Choose the minimal set of components to work with the DE10-Lite board, as shown.

Wait patiently till the installation finishes …

Next, check the option to launch USB Blaster II driver installation.

Accept the security warning and check the screen for a successful notice.

Note: you may still need to manual locate the driver when the board is plugged in the first time to your PC/laptop. Check this link for steps.

When you run the software for the first time, you will be asked to buy a full license. We will skip and run the basic lite version.

The installation is now complete. The design software is ready to compile VHDL/Verilog designs and program them onto the FPGA boards.

Next time, I will share an example of a simple design that demonstrate the basic input and output devices available on the board.

Building an extensive synchronous up/down counter with enable

2021-12-14T10:45:00+00:00

This is a popular exercise that I’d love to discuss with my students. The design is very practical and it reveals the basic idea how to generalise the ripple adder concept to create an iterative circuit for a synchronous counter. The requirement of having up or down control also challenges the understanding of the 2’s complement arithmetic which is usually introduced earlier.

The question

We want to build a up/down synchronous counter with an enable signal. The basic structure of the design is given as follows:

The design is iterative so that more bit slices which each contains a mystery block and a D-type flip-flop can be added to the end (left hand side of the diagram above) to extend the counter for more bits. But in this exercise, we focus on a 4-bit design. $Q$ is the output of the counter and it counts up (e.g. 0100, 0101, 0110, ..) and down (e.g. 0011, 0010, 0001, …) depending on the control input $up/down'$. There is also an $Enable$ signal which starts or stops the counting in either up or down mode.

So the question is now:

What should be the mystery (combinational) block?
How to connect the $up/down'$ and $enable$ to the mystery blocks to fulfill the requirement? You may add some logic gates but they should be kept as few as possible.

Let’s work on the exercise and read on when you have your solution!

Hints / the partial solution

It is not too difficult to guess that the mystery block is a full adder. So now there are three bits of input to consider (i.e. $A$, $B$, $C_{in}$).

It is useful to write down the requirement in a table, with regards to the control inputs of the counter.

+----------+--------+-----------+
| up/down' | enable |     Q     |
+==========+========+===========+
|    0     |   0    | no change |
+----------+--------+-----------+
|    0     |   1    | count down|
+----------+--------+-----------+
|    1     |   0    | no change |
+----------+--------+-----------+
|    1     |   1    | count up  |
+----------+--------+-----------+

Clearly $Q$ outputs of the flip-flops go back to input $B$. And except for the first FA, $C_{in}$ and $C_{out}$ are chained together similar to a ripple adder. Therefore I would prefer to have the same input to all As of the FAs, while a specific input to the first $C_{in}$ (let’s called it $C_{in0}$ for now).

Let’s rewrite the above table based on this:

+----------+--------+----------+
| up/down' | enable |    Q     |
+==========+========+==========+
|    0     |   0    |no change |
+----------+--------+----------+
|    0     |   1    | 1111 + 0 |
+----------+--------+----------+
|    1     |   0    |no change |
+----------+--------+----------+
|    1     |   1    | 0000 + 1 |
+----------+--------+----------+

This means that when the counter counts up, $A$ = 0 to all FAs and $C_{in0}$ = 1. Similarly $A$ = 1 and $C_{in0}$ = 0 when we count down (1111 is the 2’s complement representation of -1, isn’t it?)

You can now try to complete the table for rows 1 & 3. Then you should be able to work out the additional gates and connections required (if not, you can read on to the full solution)

The last piece of puzzle / the full solution

If we follow from the partial solution, the complete table would be:

+----------+--------+----------+
| up/down' | enable | A + Cin0 |
+==========+========+==========+
|    0     |   0    | 1111 + 1 |
+----------+--------+----------+
|    0     |   1    | 1111 + 0 |
+----------+--------+----------+
|    1     |   0    | 0000 + 0 |
+----------+--------+----------+
|    1     |   1    | 0000 + 1 |
+----------+--------+----------+

where I added a trick on the first row to add 10000 = 1111 + 1 instead of 00000. The main reason is that I would like to match the bits with the complement of the $up/down'$ signal. And from the truth table we can see that we need an XNOR gate to generate $C_{in0}$. As a conclusion:

\[\begin{matrix} A & = (up/down')'\\ C_{in0} & = (up/down') \bar{\oplus} enable\\ \end{matrix}\]

Two additional logic gates are added to complete the solution.

I will be sharing the VHDL implementation in a future post.

Building a digital circuit for addition

2021-01-15T13:38:00+00:00

First of all, digital circuits work with 0’s and 1’s (i.e. bits). Numbers are therefore represented in binary before they can be added in the digital circuits that we are going to design. For now, let’s assume numbers are non-negative $X = 0, 1, 2, \ldots$ so that a simple binary conversion suffices, for instance:

\[X = 9_{10} = 1001_{2}\] \[Y = 4_{10} = 0100_{2}\]

We add digit by digit from the least significant end (right hand side) through to the most significant end (left hand side), with possibly a carry between digits. If we denote each bit of number $X$ as $X_i$, then we need a circuit to add bits $X_i$ and $Y_i$ with a carry in $C_i$. And the circuit produces a sum bit $S_i$ and a carry out bit $C_{i+1}$, which is the carry in bit for the next digits.

The Full Adder

The behaviour of the circuit that adds the bits can be easily listed in a truth table:

$C_i$	$X_i$	$Y_i$	$C_{i+1}$	$S_i$
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

This circuit is called the full adder. And there are several interesting ways to study the truth table:

The first four rows are the cases when the carry in is 0. Extracting these rows without the first column gives you the truth table of the half adder that adds two bits and gives a sum bit and a carry bit.
The output column $C_{i+1}$ is counting two or more 1’s while the output column $S_i$ is counting odd number of 1’s.
$S_i$ and $C_{i+1}$ are two different functions of our input bits $X_i$, $Y_i$ and $S_i$.

Based on the second point above, we can derive simple Boolean equations for $S_i$ and $C_{i+1}$:

\[\begin{align} S_i &= AB + AC + BC\\ C_{i+1} &= A \oplus B \oplus C\\ \end{align}\]

If you are not familiar with exclusive OR gate as denoted by $\oplus$ you can check it out here.

Let’s give a symbol for the full adder to help our following discussion.

The arrows indicate the flow of the input bits, carry bits and the sum bits. And when there is no ambiguity the labels for the inputs/outputs are skipped in the following diagrams.

The Ripple Adder

The full adder is the circuit/device to handle addition of two bits so the remaining job is to connect the carries together, forming a chain along a list of full adders. For example, a 4-bit ripple adder is like this:

The design can be easily extended for as many bits as you want. You just need to append more full adders to the end of the chain. The more significant bits are on the left of the diagram so it matches our convention on paper. We also call this design iterative as it can be used repeatedly to construct bigger circuits for the same operation.

This gives the standard ripple adder which is used so many digital systems that involves additions and subtractions. It is imperative to note that the size (or width) of the adder, $N$ has to be decided at the time when the adder is built because the adder cannot be extended easily once it sits in the system (unless you are using programmable logic devices like FPGAs). As a result, the rule of thumb is to estimate the order of your calculations and make the adder big enough. For instance, if you intend to add numbers in a thousand range then you probably need an adder of 10-12 bits wide.

When $X$ and $Y$ are non-negative (i.e. unsigned), a carry out from your last full adder (e.g. $C_4$ in the diagram above) indicates an overflow of the $N$-bit adder. You can save the carry to preserve the correct sum or simply raise an error as you cannot go on with further additions.

For now, addition is sorted, but how about subtraction? In the next blog, I will discuss the modification required to turn a ripple adder into a subtractor using the useful 2’s complement representation.

A Trick for Subtraction

2020-12-16T09:59:00+00:00

The first series of my blogs is to explain how we build a digital circuit for addition and subtraction – the most fundamental arithmetic operations. I will start with some theory of the maths and then discuss the circuitry. The discussion is a background for us to understand the signed multiplication that I wrote earlier on.

To begin with, I would like to show a little trick on doing subtraction without really doing any subtraction at all! The example is as follows: I am asked to do

\[5 - 3\]

But suppose I do not know (or want) to subtract, so I rewrite the expression as

\[5 + (-3)\]

Then the negative of 3 is formed by taking the partner of 3 in this table, and plus 1.

0	9
1	8
2	7
3	6
4	5

Therefore, we have

\[5 - 3 = 5 + (-3) := 5 + (6 + 1) = \cancel{1}2\]

By dropping the carry (based on the fact that the difference is always less than 10), we found the difference 2 without really subtracting!

Let’s try again with another example:

\[4 - 1 = 4 + (-1) := 4 + (8 + 1) = \cancel{1}3\]

We can extend the method for bigger numbers too:

\[25 - 18 = 25 + (-18) := 25 + (81 + 1) = \cancel{1}07\]

where each of the digits of 18 had its partner looked up.

Why does it work?

The idea behind this trick is rather simple – we borrow a fixed but enough amount so that the subtraction can be turned into an easy table look up (and plus one). If you look at the table and the examples again you will notice:

\[\begin{aligned} (-3) &:= 10 - 3 = 9 - 3 + 1 &= 6 + 1\\ (-1) &:= 10 - 1 = 9 - 1 + 1 &= 8 + 1\\ (-18) &:= 100 - 18 = 99 - 18 + 1 &= 81 + 1 \end{aligned}\]

Since the table is pairing bonds of 9, the actual subtraction is replaced (or intuitively done) by the table look up. And the addition of patching 1 is to make 9 or 99 back to 10 or 100, such that the calculation is correct once the carry that we are expecting is being ignored (or discarded).

You will be now tempted to try an example when you do not have enough to subtract:

\[3 - 4 = 3 + (-4) := 3 + (5 + 1) = 9\]

There are two points to note: (1) the borrow of 10 when we look up the table is not returned in the end, so we know there is not enough to subtract; (2) 9 can be viewed as (-1) if you accept negative numbers (I will explain this further later). Anyway we can now generalise this method.

The 10’s Complement Method for Subtraction (Unsigned)

For now, I consider only unsigned numbers (i.e. zero and natural numbers). Given a number $X$ of $N$ decimal digits, we define the 10’s complement of $X$ as:

\[Tenscomp(X) = 10^N - X = (10^N - 1) - X + 1 = 9\ldots99 - X + 1\]

So the 10’s complement can be found by looking up the table above for each of the digits of $X$ followed by adding an extra one. By definition, the sum of $X$ and its 10’s complement is exactly $10^N$. And then the subtraction between two numbers $X$ and $Y$ can be expressed as:

\[X - Y = X + (10^N - Y) - 10^N = X + Tenscomp(Y) - 10^N\]

When $X\geq Y$, the sum $X + Tenscomp(Y)$ will be greater or equal to $10^N$ (i.e. we can return the borrow by ignoring the carry); otherwise we can tell that $X < Y$.

Example: 741 - 258
\[Tenscomp(258) = 741 + 1 = 742\] \[741 - 258 := 741 + 742 = \cancel{1}483\]
We return $10^3 = 1000$ in the end of the calculation.

Isn’t that it complicates the calculation?

Yes indeed, on a human perspective. But if we are to design a machine for both addition and subtraction, then we can avoid subtraction by doing a table look up followed by addition. Furthermore, the fewer digits you use the easier the look up process is. In digital circuits, as you may know, we use only two digits 0 and 1. So the table look up is now further simplified as a digit (bit) flipping ($0\rightarrow 1$ or $1\rightarrow 0$ that can be realised efficiently using an inverter. In the next blog, I will explain the application of the method in binary systems and see how to build a circuit to add or subtract.

Signed Multiplication – Part 1

2020-12-13T10:02:07+00:00

Through the years my students repeatedly confuse with the theory of the signed multiplication. They do not understand why a correction is needed when the mutliplier (i.e. $B$ in $A\times B$) is negative. This is of course complicated by the fact that negative numbers are expressed or represented by its 2’s complement so that only addition is required through the procedure.

In this short article, I am going to explain and derive the correction in signed multiplication and then discuss the implications when the theory is applied to multiplier circuit design.

The Mathematics

Let’s consider two integers $A$ and $B$. We represent them in binary using exactly $N$ bits, as bit strings $a_{N-1}a_{N-2}\ldots a_0$ and $b_{N-1}b_{N-2}\ldots b_0$ respectively. Then these representations give different numerical values depending whether it is positive or not:

\[b_{N-1}b_{N-2}\ldots b_0= \left\{ \begin{matrix} B & \mathrm{when}\ B \geq 0\\ 2^N - |B| = 2^N + B &\mathrm{when}\ B < 0\\ \end{matrix} \right.\]

To avoid subtraction in binary, we convert subtraction into a 2’s complement operation (equivalent to take a negative of a number) followed by a normal addition.

\[A - B = A + (-B)\rightarrow A + (2^N - B)\]

The carry out $2^N$ should be ignored to keep the answer numerically correct.

Now consider the binary multiplication $A\times B$ using the longhand method, where each bit $b_i$ is multiplied (or logic AND) to $a_{N-1}\ldots a_0$ and then shift $i$ bits to the left to give a signed subproduct. The subproducts $P_i$ are added together to produce the final product $P$. In order to preserve the numerical value of $A$, the additions of subproducts require $N + 1$ bit in minimum and every time the partial sum should be signed extended. In other words, the binary addition, under such conditions, is signed and safe with the 2’s complement representation. We can therefore express $P$ as:

\[P = \sum_{i=0}^{N-1} A\times 2^ib_i = A\times\sum_{i=0}^{N-1}2^ib_i\]

When $B$ is positive, it is obvious that $P = A\times B$ which is the product that we expect, in a total of $2N$ bits and in 2’s complement representation.

Nevertheless, when $B$ is negative, we can deduce that

\[P = A\times (2^N - |B|) = A\times (2^N + B) = 2^NA + AB\]

So we need to correct the answer after the binary multiplication by subtracting $2^NA$ from $P$:

\[\begin{align} P - 2^NA &= AB\\ AB &= P + 2^N(2^N - A) = P + C \end{align}\]

Subtraction is once again avoided by taking 2’s complement of $A$ in $N$ bits and shifting that $N$ bits to the left. The correction is in $2N$ bits and matches the bit width of the product $P$. We let $C = 2^N(2^N - A)$ the correction value that should be added to the product when $B$ is negative.

To conclude, the first method to correct the answer from the binary multiplication is:

\[AB = \left\{ \begin{matrix} P & \mathrm{when}\ B \geq 0\\ P + C &\mathrm{when}\ B < 0\\ \end{matrix} \right.\]

If there is a carry at bit position $2N$ (i.e. $2^{2N}$), it should be ignored.

Example 1: $N = 4, A = -6, B = -3$, then

$a = 10000_2 - 0110_2 = 1010_2 = 10$, $b = 10000_2 - 0011_2 = 1101_2 = 13$

$P = 10110010_2$ (carry discarded) which represents $-78 = -6\times 2^4 + (-6)(-3)$ $C = 2^4(2^4 - (-6)) = 16(16 + 6) = 352 = 256 + 92$ $P + C = -78 + 352 = 256 + 18 = 2^8 + 18$

So once the carry at bit 8 is discarded, the correct product is found.

Correcting the product after the binary multiplication requires a total of $N + 2$ additions ($N + 1$ for subproducts and a last one correction). This can be reduced back to $N + 1$ if we merge the correction with the last addition of subproduct, noting that:

\[P = \sum_{i=0}^{N-1} A\times 2^ib_i = \sum_{i=0}^{N-2}2^ib_i + 2^{N-1}A\]

when $B$ is negative and $b_{N-1} = 1$. Then we have:

\[\begin{aligned} AB &= P + 2^N(2^N - A) \\ &= \sum_{i=0}^{N-2}2^ib_i + 2^{N-1}A + 2^N(2^N - A)\\ &= \sum_{i=0}^{N-2}2^ib_i + 2^{N-1}(A + 2(2^N - A))\\ &= \sum_{i=0}^{N-2}2^ib_i + 2^{N-1}(2^{N+1} - A)\\ &= P' + C' \end{aligned}\]

$C'$ is the 2’s complement of $A$ in $(N+1)$ bits then shifted $(N-1)$ bits to the left. $C'$ is also $2N$ bits in width and matches that of the partial products $P'$.

This gives the second method to correct the answer from the binary multiplication:

\[AB = \left\{ \begin{matrix} P & \mathrm{when}\ B \geq 0\\ P' + C' &\mathrm{when}\ B < 0\\ \end{matrix} \right.\]

Similarly, if there is a carry at bit position $2N$ (i.e. $2^{2N}$), it should be ignored.

Example 2: $N = 4, A = -6, B = -3$

$a = 10000_2 - 0110_2 = 1010_2 = 10$, $b = 10000_2 - 0011_2 = 1101_2 = 13$

$P' = 11100010_2$, $C' = 2^3(2^5 - (-6)) = 00110000_2$ (if you convert from 560 then you need to drop the leading 10 bits and leave the least 8 bits) $P' + C' = 11100010_2 + 00110000_2 = \cancel{1}00010010_2$ which gives 18 when carry out is discarded.

In the next part, I will discuss what this mathematical analysis means to the multiplier design in digital electronics.

My new blog

2020-12-12T08:00:00+00:00

This is the first post in this new blog of mine. After teaching engineering of digital systems large and small for a decade, I feel that there are much to share with the others. While we are still in the pandemic, blogging seems to be the best way to share and communicate with other each.

In here I would like to keep things simple and easy to understand for most readers without a technical background, in the same way I would do to my students. I decided to start with many topics that confuses my students in the digital system design classes. For example, the theory behind computer arithmetic and the design of arithmetic circuits in digital technolgies. Later I will also write about interfacing between software (i.e. our programs) and hardware (i.e. our computer).

Of course I would also love to write short stories of my professional work, whenever it is related digital electronics and systems.

If you have any comments about my articles, feel free to get in touch through my contacts from the about page.

\(C_i\)	\(X_i\)	\(Y_i\)	\(C_{i+1}\)	\(S_i\)
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1